This invention relates to a room temperature wet chemical growth (RTWCG) process of SiO-based insulator coatings on semiconductor substrates including Si, Ge, III-V and I-III-VI compound semiconductors and, specifically, to the RTWCG of SiO-based films on Si in the manufacture of silicon-based electronic and photonic (optoelectronic) device applications.
The United States Government has rights in this invention pursuant to NASA Contract No. NAS3-97181.
Silicon dioxide (SiO.sub.2) forms the basis of the planar technology. In industrial practice insulator coatings for electronic and photonic devices layers are most frequently formed by thermal oxidation of Silicon (Si) in the temperature range 900 to 1200.degree. C. SiO.sub.2 is also deposited by chemical vapor deposition (CVD) techniques at lower temperatures (200 to 900.degree. C.) on various substrates.
Thermal and CVD-grown SiO.sub.2 based layers are used as diffusion masks, to passivate device junctions, as electric insulation, as dielectric material in Si technology, and as capping layers for implantation-activation annealing in III-V compound semiconductor technology, to name a few.
The growth of insulator films at low temperatures is very attractive for most device applications due to reduced capital cost, and high output and technological constraints associated with the growth of dielectric thin films using conventional high-temperature growth/deposition techniques.
Dielectric films for photonic devices are well known in the art and are usually deposited at near room temperature on various substrates using physical vapor deposition processes including conventional (nonreactive) or reactive resistive, induction or electron beam evaporation, reactive or nonreactive dc or RF magnetron and ion-beam sputtering processes.
Room temperature growth of insulator layers on semiconductor surfaces using anodic oxidation is known in the art. For silicon, using anodic oxidation up to 200 nm SiO.sub.2 layers can be grown on the underlying Si substrates. The anodic oxidation process consumes about 0.43 of the thickness of the oxide from the underlying Si substrate, and is not compatible with most metallization schemes. This limits its application as a replacement of thermal or vacuum deposited SiO.sub.2.
Deposition of SiO2 insulator layers from solutions is known in the art using organo-metallic solutions. In this procedure, the insulator layer is applied onto the substrate either by dipping the substrate into the solution or by spinning the substrate after a small amount of the solution is applied onto the surface. In both cases the substrate is then placed in an oven to drive off the solvent.
Researchers from Japan, China and Taiwan describe processes for deposition of SiO.sub.2 and SiO.sub.2-x F.sub.x layers on glass and silicon surfaces using a room temperature (30 to 50.degree. C.) solution growth. The growth of liquid-phase deposited (LPD) SiO.sub.2, initially proposed by Thomsen et al. for deposition of SiO.sub.2 on the surface of soda lime silicate glass, is based on the chemical reaction of H.sub.2 SiF.sub.6 with water to form hydrofluoric acid and solid SiO.sub.2. The initial H.sub.2 SiF.sub.6 solution is saturated with SiO.sub.2 powder (usually in a sol-gel form). Before immersing the glass into the solution, a reagent that reacts with the hydrofluorosilicilic acid, such as boric acid, was added to the solution. Boric acid reacts with the hydrofluorosilicilic acid and makes the solution supersaturated with silica.
One of the major disadvantages of SiO.sub.2 LPD method described above is a very low deposition rate of about 8 nm/hour to about 24 nm/hour, which makes it impractical for growing insulator layers for most semiconductor device applications. Deposition rates of up to 110 nm/hour are claimed by Ching-Fa Yeh et al. in the hydrofluorosilicilic acid-water system and the composition of the resulting films was reported to be SiO.sub.2-x F.sub.x where x is about 2%. our own experimentation using the LPD method, seems to indicate that the LPD SiO.sub.2 has poor adhesion to the Si surfaces, and the maximum growth rate we obtained is smaller than the reported values (less than 25 nm/hour). Even assuming that the reported 110 nm/hour deposition rates are possible, these deposition rates are still too low since assuming that the deposition rate is constant with the deposition time, it will require about 9 hours to deposit an oxide with a thickness of about 1 .mu.m needed for ULSI interlevel dielectric.
The term RTWCG process of SiO-based insulator layers as used herein means a room temperature (e.g., 10.degree. C.-40.degree. C.) wet chemical growth process of Si.sub.x O.sub.y X.sub.z (SiOX) layers where x is from 0.9 to 1.1, y is from 0.9 to 1.9 and z is from 0.01 to 0.2, where Si stands for silicon, 0 stands for oxygen, and X is either fluorine (F), carbon (C) or a combination of these with iron (Fe), palladium (Pd), or titanium (Ti) contaminants, depending on the redox system being used.